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Semiconductor
MSM5117405D
This version:Apr.1999
4,194,304-Word 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
DESCRIPTION
The MSM5117405D is a 4,194,304-word 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5117405D achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117405D is available in a 26/24-pin plastic SOJ, 26/24-pin plastic TSOP.
FEATURES
* * *
* * *
4,194,304-word 4-bit configuration Single 5V power supply, 10% tolerance Input
Output Refresh
: TTL compatible, low input capacitance
: TTL compatible, 3-state : 2048 cycles/32 ms
Fast page mode, read modify write capability
*
* *
CAS before RAS refresh, hidden refresh, RAS-only refresh capability
Multi-bit test mode capability Package options:
26/24-pin 300mil plastic SOJ 26/24-pin 300mil plastic TSOP
(SOJ26/24-P-300-1.27) (TSOPII26/24-P-300-1.27-K) (TSOPII26/24-P-300-1.27-L)
(Product : MSM5117405D-xxSJ) (Product : MSM5117405D-xxTS-K) (Product : MSM5117405D-xxTS-L) xx : indicates speed rank.
PRODUCT FAMILY
Family MSM5117405D-50 MSM5117405D-60 MSM5117405D-70 Access Time (Max.) tRAC 50ns 60ns 70ns tAA 25ns 30ns 35ns tCAC 13ns 15ns 20ns tOEA 13ns 15ns 20ns Cycle Time (Min.) 84ns 104ns 124ns Power Dissipation Operating (Max.) 550mW 495mW 440mW 5.5mW Standby (Max.)
1/15
MSM5117405D
PIN CONFIGRATION (TOP VIEW)
VCC DQ1 DQ2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS VCC DQ1 DQ2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 19 18 17 16 15 14 VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS VSS DQ4 DQ3 CAS OE A9 A8 A7 A6 A5 A4 VSS 26 25 24 23 22 21 19 18 17 16 15 14 1 2 3 4 5 6 8 9 10 11 12 13 VCC DQ1 DQ2 WE RAS NC A10 A0 A1 A2 A3 VCC
A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13
A10 8 A0 9 A1 10 A2 11 A3 12 VCC 13
26/24-Pin Plastic SOJ
26/24-Pin Plastic TSOP (K Type)
26/24-Pin Plastic TSOP (L Type)
Pin Name A0 - A10 RAS CAS DQ1 - DQ4 OE WE VCC VSS NC
Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5V) Ground (0V) No Connection
Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.
2/15
MSM5117405D
BLOCK DIAGRAM
RAS CAS
Timing Generator Timing Generator Write Clock Generator 4 Internal Address Counter Row Address Buffers Refresh Control Clock Sense Amplifiers 4 I/O Selector 4 4 Input Buffers 4
WE OE
Output Buffers 4 4
11
Column Address Buffers
11
Column Decoders
A0 - A10
DQ1 - DQ4
11
11
Row Decoders
Word Drivers
Memory Cells
VCC
On Chip VBB Generator On Chip IVCC Generator
VSS
3/15
MSM5117405D
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Voltage VCC supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT VCC IOS PD* Topr Tstg *: Ta = 25C Rating -0.5 to VCC + 0.5 -0.5 to 7.0 50 1 0 to 70 -55 to 150 Unit V V mA W C C
Recommended Operating Conditions
(Ta = 0C to 70C)
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. 4.5 0 2.4 -0.5
*2
Typ. 5.0 0 3/4 3/4
Max. 5.5 0
Unit V V V V
VCC VSS VIH VIL
VCC + 0.5*1
0.8
Notes:
*1. The input voltage is VCC + 2.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 2.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied).
Capacitance
(VCC = 5V 10%, Ta = 25C, f=1MHz)
Parameter Input Capacitance (A0 - A10) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol Typ. 3/4 3/4 3/4 Max. 5 7 7 Unit pF pF pF
CIN1 CIN2 CI/O
4/15
MSM5117405D
DC Characteristics
(VCC = 5V 10%, Ta = 0C to 70C)
MSM5117405 MSM5117405 MSM5117405 D-50 D-60 D-70 Unit Min. Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) VOH VOL IOH = -5.0mA IOL = 4.2mA 0V VI 6.5V ; ILI All other pins not under test = 0V DQ disable 0V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC - 0.2V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. 3/4 100 3/4 90 3/4 80 mA 1,3 3/4 5 3/4 5 3/4 5 mA 1 3/4 100 3/4 90 3/4 80 mA 1,2 -10 10 -10 10 -10 10 mA 2.4 0 Max VCC 0.4 Min. 2.4 0 Max VCC 0.4 Min. 2.4 0 Max VCC 0.4 V V
Parameter
Symbol
Condition
Note
ILO
-10
10
-10
10
-10
10
mA
ICC1
3/4 3/4 3/4
100
3/4 3/4 3/4
90
3/4 3/4 3/4
80
mA
1,2
2 1
2 1
2 1 mA 1
ICC6
3/4
100
3/4
90
3/4
80
mA
1,2
Notes: 1. 2. 3.
ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH.
5/15
MSM5117405D
AC Characteristic (1/2)
(VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3,11,12
Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Symbol tRC tRWC tPC MSM5117405 D-50 Min. 84 110 20 58 3/4 3/4 3/4 3/4 3/4 0 5 0 0 0 0 1 3/4 30 50 50 7 7 7 7 35 5 30 5 11 9 Max. 3/4 3/4 3/4 3/4 50 13 25 30 13 3/4 3/4 13 13 13 13 50 32 3/4 10,000 100,000 3/4 3/4 3/4 10,000 3/4 3/4 3/4 3/4 37 25 MSM5117405 D-60 Min. 104 135 25 68 3/4 3/4 3/4 3/4 3/4 0 5 0 0 0 0 1 3/4 40 60 60 10 10 10 10 40 5 35 5 14 12 Max. 3/4 3/4 3/4 3/4 60 15 30 35 15 3/4 3/4 15 15 15 15 50 32 3/4 10,000 100,000 3/4 3/4 3/4 10,000 3/4 3/4 3/4 3/4 45 30 MSM5117405 D-70 Min. 124 160 30 78 3/4 3/4 3/4 3/4 3/4 0 5 0 0 0 0 1 3/4 50 70 70 13 13 10 13 45 5 40 5 14 12 Max. 3/4 3/4 3/4 3/4 70 20 35 40 20 3/4 3/4 20 20 20 20 50 32 3/4 10,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns 7,8 7,8 7 7 3 4,5,6 4,5 4,6 4 4 4 Unit Note
Fast Page Mode Read Modify Write t HPRWC Cycle Time tRAC Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS Data Output Hold After CAS Low CAS to Data Output Buffer Turn-off Delay Time RAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time WE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge OE Hold Time from CAS (DQ Disable) RAS to CAS Delay Time RAS to Column Address Delay Time tCAC tAA tCPA tOEA tCLZ tDOH tCEZ tREZ tOEZ tWEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tCHO tRCD tRAD
100,000 ns 3/4 3/4 3/4 10,000 3/4 3/4 3/4 3/4 50 35 ns ns ns ns ns ns ns ns ns ns 5 6
6/15
MSM5117405D
AC Characteristic (2/2)
(VCC = 5V 10%, Ta = 0C to 70C) Note1,2,3,11,12
Parameter Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width WE Pulse Width (DQ Disable) OE Command Hold Time OE Precharge Time OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode)
Symbol
MSM517405 D-50 Min. Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 7 0 7 25 0 0 0 0 7 7 7 7 7 7 7 7 0 7 13 30 42 67 47 5 5 10 10 10 10 10
MSM5117405 D-60 Min. 0 10 0 10 30 0 0 0 0 10 10 10 10 10 10 10 10 0 10 15 34 49 79 54 5 5 10 10 10 10 10 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
MSM5117405 D-70 Min. 0 13 0 13 35 0 0 0 0 13 10 10 13 10 10 13 13 0 13 20 44 59 94 64 5 5 10 10 10 10 10 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tWPE tOEH tOEP tOCH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWTH
9 9 10
11 11
10 10 10 10
7/15
MSM5117405D
Notes:
1.
A start-up delay of 200ms is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. The AC characteristics assume tT = 2ns. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. tCEZ (Max), tREZ (Max), tWEZ (Max), tOEZ (Max) define the time at which the output achived the open circuit condition and are not referenced to output voltage levels. tCEZ and tREZ must be satisfied for open circuit condition. tRCH or tRRH must be satisfied for a read cycle.
2. 3.
4. 5.
6.
7.
8. 9.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheets is a 2-bit parallel test function, CA0 and CA1 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
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MSM5117405D
Timing Chart
x Read Cycle
tRC tRAS tRP tCRP tCSH tRCD tRAD tRAL tASR tRAH tASC
Column
VIH RAS VIL
CAS
VIH VIL
tRSH tCAS
tCRP
tCAH
Address
VIH VIL VIH VIL VIH VIL
Row
tRCS tAA tROH tAOE tCAC tRAC
tRRH tRCH tREZ
WE
OE
tOEZ tCLZ
Valid Data-out
tCEZ
DQ
VOH VOL
Open
"H" or "L" x Write Cycle (Early Write)
RAS
VIH VIL tCRP tRCD tRAD
tRC tRAS tRP tCSH tRSH tCAS tRAL tCRP
CAS
VIH VIL tASR
tRAH
tASC
tCAH
Address
VIH VIL
Row
Column
tCWL tWCS tWP tWCH
WE
VIH VIL VIH VIL VIH VIL
tRWL
OE
tDS
Valid Data-in
tDH
Open
DQ
"H" or "L"
<248
MSM5117405D x Read Modify Write Cycle
tRWC tRAS tRP tCSH tRCD tRAD tRSH tCAS tCWL tRWL tCRP
RAS
VIH VIL tCRP
CAS
VIH VIL tASR
tRAH
tASC
Column
tCAH
Address
VIH VIL
Row
tRCS tRWD
tCWD
tWP
WE
VIH VIL VIH VIL tRAC tCLZ tCAC tOEZ
Valid Data-out
tAWD tAA tOEA tOED tDH tDS
Valid Data-in
tOEH
OE
DQ
VI/OH VI/OL
"H" or "L"
43248
MSM5117405D x Fast Page Mode Read Cycle (Part-1)
tRASP RAS VIH VIL tCRP CAS VIH VIL VIH VIL VIH VIL VIH VIL tOEA tCAC DQ VOH VOL tCLZ tAA tRAC tAA tCPA tDOH
Valid Data-out
tRP tHPC tRHCP tCP tCAS tCAS tASC tCAH
tRCD tCSH tCAS tASR
Row
tCP
tRAD tRAH tASC
tCAH
tASC
Column
tCAH
Address
Column
Column
tRCS WE tCHO tOEP tCAC tAA tOEA tOEZ
Valid Data-out
tOCH tOEP tOEA
tRRH
tCAC
OE
tOEZ
Valid * Data-out
tREZ
Valid * Data-out
* : Same Dada,
"H" or "L"
x
Fast Page Mode Read Cycle (Part-2)
tRASP RAS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tCAC tCAC DQ VOH VOL tCLZ tWEZ
Valid * Data-out
tRP tHPC tRHCP tCP tCAS tASC
Column
tRCD tCRP tCSH tCAS tASR
Row
tCP
tCAS tCAH
Column
CAS
tRAD tRAH tASC
tCAH
tASC
tCAH
Address
Column
tRCS WE tAA tRAC
tRCS tRCH tWPE tOEA
tAA
tCPA tAA
OE
tCAC
tDOH
Valid * Data-out
tCEZ
Valid * Data-out
* : Same Dada,
"H" or "L"
44248
MSM5117405D x Fast Page Mode Write Cycle (Early Write)
tRASP RAS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tDS DQ VIH VIL
Valid * Data-in
tRP tHPC tHPC tCP tCAS tRSH tCAS tCAH
tCSH tCRP tRCD tCAS tASR
Row
tCP
CAS
tRAD tRAH tASC
tCAH
tASC
tCAH
tASC
Address
Column
Column
Column
tWCS
tWCH
tWCS
tWCH
tWCS tWCH
WE
OE
tDH
tDS
Valid * Data-in
tDH
tDS
Valid * Data-in
tDH
"H" or "L"
x
Fast Page Mode Read Modify Write Cycle
tRASP VIH RAS VIL VIH VIL tASR Address VIH VIL VIH VIL tRAC OE VIH VIL tCAC DQ VI/OH VI/OL tCLZ tOEZ
9DOLG#'DWD0RXW
tRWD tCRP tRCD tCWD tRAD tRAH
Column
tCPWD tCP tASC tHPRWC tCAH tCWL
Column
tRWL
CAS
tASC
tCAH tCPA
Row
tRCS WE tAWD tAA tOEA tOED tDH tDS
tRCS
tCWD tAWD
tWP
tDS
tWP
tOEH tCAC tCLZ tOEZ
9DOLG#'DWD0LQ
tOED tDH
9DOLG#'DWD0RXW
tOEH
9DOLG#'DWD0LQ
"H" or "L"
45248
MSM5117405D x RAS-Only Refresh Cycle
tRC RAS VIH VIL VIH VIL VIH VIL VOH VOL tASR tRAH
Row
tRAS tRP tCRP tRPC
CAS
Address
tCEZ DQ
Open
Note: WE, OE = "H" or "L"
"H" or "L"
x
CAS before RAS Refresh Cycle
tRP RAS VIH VIL VIH VIL tCEZ DQ VOH VOL tRPC tCP tCSR tCHR tRAS
tRC tRP tRPC
CAS
Open
Note: WE, OE, Address = "H" or "L"
46248
MSM5117405D x Hidden Refresh Read Cycle
tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAD tRAH
Row
tRC tRAS tRSH tRP tCHR tRP
tRAS tCRP tRCD
CAS
tASC
Column
tCAH
tRCS WE
tCAC tRAL tAA tROH tOEA
tRRH
tWRH tWRP
OE
VIH VIL
tOEZ DQ VOH VOL
Open
tRAC
tCLZ
Valid Data-out
"H" or "L" x Hidden Refresh Write Cycle
tRC RAS VIH VIL VIH VIL tASR Address VIH VIL tRAD tRAH
Row
tRC tRAS tRSH tRP tCHR tRP
tRAS tCRP tRCD
CAS
tASC
Column
tCAH
tRAL tRWL tWP tWCS tWCH
WE
VIH VIL VIH VIL VIH VIL tDS
OE
tDH
Valid Data-in
DQ
"H" or "L"
47248
MSM5117405D CAS before RAS Self-Refresh Cycle
tRP RAS VIH VIL VIH VIL tCEZ DQ VOH VOL tRCP tCP CAS tCSR
tPASS
tRPS
tRPC tCHS
Open
Note: WE, OE, Address = "H" or "L" Only SL Version
"H" or "L"
48248

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